With the advances of semiconductor and computer technology, computer systems are becoming faster and at the same time smaller in size. Desk-top and even lap-top computer systems now possess processing speeds of main-frame computers that used to fill up a small room. Even hand-held computer systems such as personal digital assistants (PDA), which are becoming more popular, are getting more powerful. As computer systems become more miniaturized and inexpensive, more demands are constantly being required of them as well. One such demand is speed.
To increase the speed of computer systems, a decentralized approach has been implemented in their design. Within each computer system there are many integrated circuits (IC) designed to perform dedicated functions such as a memory controller, a hard disk controller, a graphics/video controller, a communications controller, and other peripheral controllers. These dedicated integrated circuits can simultaneously perform the different functions independently. Such decentralized approach minimizes "bottlenecks" and therefore helps improve the speed of computer systems.
Even so, the tasks performed by these dedicated integrated circuits, such as graphics and video processing, are becoming increasingly more time-consuming and complex. In graphics and video processing, even a simple task may require executing numerous number of steps. As an example, consider the task of moving a 3 dimensional (3D) graphics object from one position to another position on the display screen. In addition to retrieving the attribute data related to the object (e.g., height, width, color, texture, etc.) from memory (e.g., a frame buffer) and computing the distances between the source and destination positions, the graphics controller must also compute the new color and texture values for the object's pixels to accurately reflect the object's shading at the new position. Accordingly, the graphics controller must perform all these steps in response to this "move" command. While the graphics controller carries out these steps, it is busy and therefore can not execute another command. Meanwhile, additional commands may be generated by the computer user, for example, to further manipulate the graphics objects in this frame buffer. Thus, depending on the processing power of the graphics controller, a long queue of commands is likely to result. Conventionally, these commands are stored in a buffer memory that is external to the graphics controller, to await: for their turn to be executed. However, this requires the host. processor to periodically interrupt or poll the graphics controller to determine whether it is ready for the next command. Such interruption and polling requires a lot of the host processor's time which makes it unavailable for other tasks thereby slowing down the computer system as a whole. In addition, the time required to access the stored commands in the external buffer memory is another important disadvantage.
To help speed up this bottleneck, a First-In-First-Out (FIFO) buffer is implemented inside the graphics controller to store new commands generated while the graphics controller is still busy executing the previous command. The implementation of an internal FIFO buffer means that the host processor no longer needs to interrupt or poll the graphics controller thereby reducing the host processor overhead. The fact that the FIFO buffer is embedded (i.e., internal) in the graphics controller further means that the FIFO buffer access time is reduced. However, the size of the internal FIFO buffer is very much restricted because it takes up valuable space on the IC chip which results in less functions being implemented in the IC circuit. Accordingly, the internal command FIFO buffer is restricted to storing only three or four commands at any one time. Given the complexity of the tasks that current computer systems are required to perform (e.g., graphics) and therefore the command queue involved, such command FIFO BUFFER is inadequate at best and would result in the host processor having to wait for the FIFO buffer to become available.
Thus, a need exists for an apparatus, system, and method that allows for high capacity and fast access command queuing without requiring excessive host processor overhead.